ADE7518
Table 38. Interrupt Status 2 SF R (MIRQSTM, 0xDD)
Bit
7
6
5
4
3
2
1
0
Interrupt Flag
CF2
CF1
VAEOF
REOF
AEOF
VAEHF
REHF
AEHF
Description
Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not
enabled by clearing Bit 2 of the MODE1 register.
Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if the CF1 pulse output is not
enabled by clearing Bit 1 of the MODE1 register.
Logic 1 indicates that the VAHR register has overflowed.
Logic 1 indicates that the VARHR register has overflowed.
Logic 1 indicates that the WATTHR register has overflowed.
Logic 1 indicates that the VAHR register is half full.
Logic 1 indicates that the VARHR register is half full.
Logic 1 indicates that the WATTHR register is half full.
Table 39. Interrupt Status 3 SF R (MIRQSTH, 0xDE)
Bit
7
6
5
4
3
2
1
0
Interrupt Flag
RESET
Reserved
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Description
Indicates the end of a reset (for both software and hardware reset).
Reserved.
Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).
Logic 1 indicates that the current channel has exceeded the IPKLVL value
Logic 1 indicates that the voltage channel has exceeded the VPKLVL value.
Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.
Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles.
Logic 1 indicates detection of a zero crossing in the voltage channel.
Table 40. Interrupt Enable 1 SF R (MIRQENL, 0xD9)
Bit
7 to 5
4
3
2
1
0
Interrupt Enable Bit
Reserved
VARSIGN
APSIGN
VANOLOAD
RNOLOAD
APNOLOAD
Description
Reserved.
When this bit is set, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
Table 41. Interrupt Enable 2 SF R (MIRQENM, 0xDA)
Bit
7
6
5
4
3
2
1
0
Interrupt Enable Bit
CF2
CF1
VAEOF
REOF
AEOF
VAEHF
REHF
AEHF
Description
When this bit is set, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
Table 42. Interrupt Enable 3 SF R (MIRQENH, 0xDB)
Bit
7 to 6
5
4
3
2
1
0
Interrupt Enable Bit
Reserved
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Description
Reserved.
When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.
Rev. 0 | Page 39 of 128
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